Fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The components are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench which is generally wider than the contact hole in an upper portion. The via serves as a contact to a component while the trench contains the conductive line for connecting the component to, for example, other component.
To increase throughput, a plurality of ICs are fabricated on a wafer in parallel. The ICs are separated into individual chips in a process typically referred to as “dicing”. Due to the properties of the typical dielectric layer, cracks propagate from the area where dicing tool cuts the wafer into the active chip areas, causing reliability and yield issues. Therefore, crack-stop regions are introduced to reduce the crack propagation during dicing. However, the stress generated by metal lines often causes delamination of the metal lines in the crack-stop regions.
From the foregoing discussion, it is desirable to prevent delamination of metal lines at the crack-stop (CS) regions.